1. Field of the Invention
An invention described in this specification relates to a technology for driving a self-light-emitting device of a current-driven type. It is to be noted that an embodiment of the present invention is applied to a display panel module whereas another embodiment of the present invention is applied to a variety of electronic apparatus each employing the display panel module.
2. Description of the Related Art
The following description explains the structure of an organic EL (Electro Luminescence) panel module adopting an active matrix driving method as the structure of a typical display panel module and typical operations carried out by the organic EL panel module.
FIG. 1 is an explanatory block diagram showing a typical system structure of the organic EL panel module serving as a typical display panel module 1. As shown in the block diagram, the display panel module 1 employs a pixel array section 3, a signal-line driving section 5, a first control-line driving section 7 and a second control-line driving section 9. Each of the signal-line driving section 5, the first control-line driving section 7 and the second control-line driving section 9 is a circuit for driving the pixel array section 3.
In the pixel array section 3, each of pixels serves as a white unit. The pixels are laid out on the screen, which is formed by the pixel array section 3, to form a two dimensional matrix at resolutions prescribed in the vertical and horizontal directions.
FIG. 2 is an explanatory block diagram showing the configuration of a pixel which includes an array of sub-pixels 11 to serve as a white unit as described above. In the case of the configuration shown in the block diagram of FIG. 2, the pixel is configured to serve as a set which has an R (red color) sub-pixel 11, a G (green color) sub-pixel 11 and a B (blue color) sub-pixel 11. The number of sub-pixels 11 laid out on the pixel array section 3 is thus M×N×3 where reference notation N denotes the number of sub-pixels laid out on each row of the two dimensional matrix whereas reference notation M denotes the number of such rows laid out to form the two dimensional matrix. That is to say, the integer M represents the vertical-direction (or Y-direction) resolution whereas the integer N represents the horizontal-direction (or X-direction) resolution.
FIG. 1 shows interconnections between the circuits for driving the pixel array section 3 and the sub-pixels 11 which each serve as a smallest unit of the structure of each of the pixels composing the pixel array section 3.
The signal-line driving section 5 is a driving circuit for asserting a signal electric potential Vsig representing pixel data Din on a data signal line DTL. Each of the signal lines DTL is stretched in the vertical direction (or the Y direction). On the screen formed by the pixel array section 3, 3N signal lines DTL are laid out in the horizontal direction (or the X direction).
The first control-line driving section 7 is a driving circuit for driving write control signal lines WSL in order to sequentially control operations to write the signal electric potential Vsig or the like into sub-pixels 11 on a line-after-line basis. In the case of the display panel module 1 shown in the block diagram of FIG. 1, the first control-line driving section 7 sequentially carries out operations for each horizontal line unit (or each row of the two dimensional matrix) on a line-after-line basis in order to specify timings to write the signal electric potentials Vsig and offset electric potentials Vofs into sub-pixels 11.
The control-line driving section 9 is a driving circuit for controlling switching from an operation to supply a driving power to sub-pixels 11 through lighting control signal lines LSL to an operation to supply no driving power to sub-pixels 11 and vice versa. To put it more concretely, the second control-line driving section 9 asserts a high-level driving electric potential Vcc or a low-level driving electric potential Vss on the lighting control signal lines LSL. The driving electric potential Vcc is also referred to as a light emission electric potential whereas the ground electric potential Vss is referred to as a no-light emission electric potential.
In the case of the display panel module 1 shown in the block diagram of FIG. 1, each of the write control signal lines WSL and the lighting control signal lines LSL is stretched in the X direction (or the horizontal direction). 3M write control signal lines WSL are laid out in the Y direction (or the vertical direction). By the same token, 3M lighting control signal lines LSL are also laid out in the Y direction (or the vertical direction) as well.
FIG. 3 is an explanatory circuit diagram showing the structure of a sub-pixel 11. As shown in the circuit diagram of FIG. 3, the sub-pixel 11 employs a signal sampling transistor N1, a device driving transistor N2, a signal holding capacitor Cs and an organic EL device OLED. Each of the signal sampling transistor N1 and the device driving transistor N2 is a thin film transistor. The signal holding capacitor Cs is a capacitor for holding the gradation information supplied by the data signal line DTL.
One of the two main electrodes of the device driving transistor N2 is connected to the lighting control signal line LSL whereas the other main electrode of the device driving transistor N2 is connected the anode of the organic EL device OLED.
It is to be noted that, in the case of the sub-pixel 11 shown in the circuit diagram of FIG. 3, each of the signal sampling transistor N1 and the device driving transistor N2 is a thin-film transistor of the N-channel type. The circuit diagram of FIG. 3 also shows capacitors Coled and Csub each drawn by making use of a dashed line. The device capacitor Coled represents the capacitance of the organic EL device OLED whereas the parasitic capacitor Csub is a parasitic capacitor which exists between the device capacitor Coled and a substrate. Patent Document 1:    Japanese Patent Laid-Open No. 2003-271095 Patent Document 2:    Japanese Patent Laid-Open No. 2003-255897 Patent Document 3:    Japanese Patent Laid-Open No. 2005-173434 Patent Document 4:    Japanese Patent Laid-Open No. 2006-215213